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# Name I/O Use
1 +5V 3-T regulator voltage supply (about +8V)
2 Dito
3 GND
4 READYA System ready (10K pull-up to +5V)
5 GND
6 RESET* > System reset (active low)
7 GND
8 SCLK nc System clock (not connected)
9 LCP* nc CPU indicator 1=TI99 0=2nd generation (not connected)
10 AUDIO < Input audio (=AUDIOIN)
11 RDBENA* < Active low: enable flex cable data bus drivers (1K pull-up)
12 PCBEN H PCB enable for burn-in (always High)
13 HOLD* H Active low CPU hold request (always High)
14 IAQHA nc IAQ [or] HOLDA (logical or)
15 SENILA* H Interrupt level A sense enable (always High)
16 SENILB* H Interrupt level B sense enable (always High)
17 INTA* < Active low interrupt level A (=EXTINT*)
18 LOAD* nc Unmaskable interrupt (not connected)
19 D7 <> Data bus, bit 7 (least significant)
20 GND
21 D5 <>
22 D6 <>
23 D3 <>
24 D4 <>
25 D1 <>
26 D2 <>
27 GND
28 D0 <> Data bus, bit 0 (most significant)
29 A14 >
30 A15 > Address bus, lsb. Also CRU output bit.
31 A12 >
32 A13 >
33 A10 >
34 A11 >
35 A8 >
36 A9 >
37 A6 >
38 A7 >
39 A4 >
40 A5 >
41 A2 >
42 A3 >
43 A0 > Address but, bit 0 (most significant)
44 A1 >
45 AMB H Extra address bit. Always High.
46 AMA H Extra address bit. Always High.
47 GND
48 AMC H Extra address bit. Always High.
49 GND
50 CLKOUT* > Inversion of phase 3 clock (=PHI3*)
51 CRUCLK* > Inversion of TMS9900 CRUCLOCK pin
52 DBIN > Active high = read memory
53 GND
54 WE* > Write Enable (derived from TMS9900 WE* pin)
55 CRUIN < CRU input bit to TMS9900
56 MEMEN* > Memory access enable (active low)
57 -12 Volts 3-T regulator supply voltage (about -16V)
58 Dito
59 +12 Volts 3-T regulator supply voltage (about +16V)
60 Dito